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cy2xp24 crystal to lvpecl clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-15705 rev. *g revised april 7, 2011 features one lvpecl output pair selectable output frequency: 156.25 mhz or 187.5 mhz external crystal frequency: 25 mhz low root mean square (rms) phase jitter at 156.25 mhz, using 25 mhz crystal (1.875 mhz to 20 mhz): 0.33 ps (typical ) pb-free 8-pin thin shrunk small outline package (tssop) package supply voltage: 3.3 v or 2.5 v commercial and industrial temperature ranges functional description the cy2xp24 is a pll (phase locked loop) based high performance clock generator. it is optimized to generate 10 gb ethernet, fibre channel, and other high performance clock frequencies. it produces an output frequency that is either 6.25 times or 7.5 times the crystal frequency. it uses cypress?s low noise vco technology to achieve low phase jitter, that meets both 10 gb ethernet, fibre channel, and sata jitter requirements. the cy2xp24 has a crystal oscillator interface input and one lvpecl output pair. logic block diagram /4 phase detector crystal oscillator vco 0 = /25 1 = /30 f_sel external crystal xout xin clk clk# [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 2 of 12 contents pinouts .............................................................................. 3 frequency table ............................................................... 4 absolute maximum conditions ....................................... 4 operating conditions ....................................................... 4 dc electrical characteristics .......................................... 4 ac electrical characteristics ........................................... 5 recommended crystal specifications ............................ 5 parameter measurements ................................................ 6 application information ................................................... 7 power supply filtering techni ques ............................. 7 termination for lvpecl output .................................. 7 crystal input interface ................................................. 7 ordering information ........................................................ 8 ordering code definition ....... ...................................... 8 acronyms ........................................................................ 10 document conventions ................................................. 10 units of measure ....................................................... 10 sales, solutions, and legal information ...................... 12 worldwide sales and design s upport ......... .............. 12 products .................................................................... 12 psoc solutions ......................................................... 12 [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 3 of 12 pinouts figure 1. pin diagram - 8 pin tssop 1 2 36 7 8 xout xin f_sel vss vdd clk# 45 vdd clk table 1. pin definitions - 8 pin tssop pin name type description 1, 8 vdd power 3.3 v or 2.5 v power supply. all supply current flows through pin 1 2 vss power ground 3, 4 xout, xin xtal output and input parallel resonant crystal interface 5 f_sel cmos input frequency select. when high, the output frequency is 7.5 times of the crystal frequency. when low, the out put frequency is 6.25 times of the crystal frequency 6,7 clk#, clk lvpecl output di fferential clock output [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 4 of 12 frequency table inputs pll multiplier value output frequency (mhz) crystal frequency (mhz) f_sel 25 1 7.5 187.5 25 0 6.25 156.25 absolute maximum conditions parameter description condition min max unit v dd supply voltage ? ?0.5 4.4 v v in [1] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, vtorage non operating ?65 150 ? c t j temperature, junction ? 135 ? c esd hbm esd protection (human body model) jedec std 22-a114-b 2000 ? v ul?94 flammability rating at 1/8 in. v?0 ? ja [2] thermal resistance, junction to ambient 0 m/s airflow 100 ? c / w 1 m/s airflow 91 2.5 m/s airflow 87 operating conditions parameter description min max unit v dd 3.3 v supply voltage 3.135 3.465 v 2.5 v supply voltage 2.375 2.625 v t a ambient temperature, commercial 0 70 ? c ambient temperature, industrial -40 85 ? c t pu power-up time for all v dd to reach minimum specified voltage (ensure power ramps are monotonic) 0.05 500 ms note 1. the voltage on any input or i/o pin cannot exceed the power pin during power up. power supply sequencing is not required. 2. simulated using apache sentinel ti software. the board is deri ved from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper pla nes, while the top and bottom layers have 50% metalization. no via s are included in the model. dc electrical characteristics parameter description test conditions min typ max unit i dd power supply current with output unterminated v dd = 3.465 v, f out = 187.5 mhz, output unterminated ??125v v dd = 2.625 v, f out = 187.5 mhz, output unterminated ??120v i ddt power supply current with output terminated v dd = 3.465 v, f out = 187.5 mhz, output terminated ??150v v dd = 2.625v, f out = 187.5 mhz, output terminated ??145v v oh lvpecl output high voltage v dd = 3.3 v or 2.5 v, r term = 50 ? to v dd ? 2.0 v v dd ?1.15 ? v dd ?0.75 v v ol lvpecl output low voltage v dd = 3.3 v or 2.5 v, r term = 50 ? to v dd ? 2.0 v v dd ?2.0 ? v dd ?1.625 v v od1 lvpecl peak-to-peak output voltage swing v dd = 3.3 v or 2.5 v, r term = 50 ? to v dd ? 2.0 v 600 ? 1000 mv [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 5 of 12 v od2 lvpecl output voltage swing (v oh - v ol ) v dd = 2.5 v, r term = 50 ? to v dd ? 1.5 v 500 ? 1000 mv v ocm lvpecl output common mode voltage (v oh + v ol )/2 v dd = 2.5 v, r term = 50 ? to v dd ? 1.5 v 1.2 ? ? v v ih input high voltage 0.7 x v dd ?v dd + 0.3 v v il input low voltage ?0.3 ? 0.3 x v dd v i ih input high current f_sel = v dd ??115a i il input low current f_sel = v ss ?50 ? ? a c in [3] input capacitance, f_sel ? 15 ? pf c inx [3] pin capacitance, xin & xout ? 4.5 ? pf dc electrical characteristics (continued) parameter description test conditions min typ max unit ac electrical characteristics [4] parameter description conditions min typ max unit f out output frequency 156.25 ? 187.5 mhz t r , t f [5] output rise/fall time 20 % to 80 % of full swing ? 0.5 1.0 ns t jitter( ? ) [6] rms phase jitter (random) 156.25 mhz, (1.875 ? 20 mhz), 3.3 v ? 0.33 ? ps 156.25 mhz, (12 khz ? 20 mhz), 3.3 v ? 0.6 ? ps t dc [7] duty cycle measured at zero crossing point 45 ? 55 % t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min.) ?? 5 ms t lfs re-lock time time for clk to reach valid frequency from f_sel pin change ?? 1 ms recommended crystal specifications [7] parameter description min max unit mode mode of oscillation fundamental f frequency 25 25 mhz esr equivalent series resistance ? 50 ? c 0 shunt capacitance ? 7 pf notes 3. not 100% tested, guaranteed by design and characterization. 4. characterized using an 18 pf parallel resonant crystal. 5. refer to figure 7 on page 7 . 6. refer to figure 4 on page 4. 7. refer to figure 7 on page 7 . [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 6 of 12 parameter measurements figure 2. 3.3 v output load ac test circuit figure 3. 2.5 v output load ac test circuit figure 4. output dc parameters figure 5. output rise and fall time figure 6. rms phase jitter scope v dd v ss lvpecl 50 ? 50 ? z = 50 ? z = 50 ? clk# clk 2v -1.3v +/- 0.165v scope v dd v ss lvpecl 50 ? 50 ? z = 50 ? z = 50 ? clk# clk 2v -0.5v +/- 0.125v clk v a v b clk# v od v ocm = (v a + v b )/2 20% 80% t r clk 20% 80% clk# t f phase noise phase noise mark offset frequency f1 f2 rms jitter = area under the masked phase noise plot noise power [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 7 of 12 figure 7. output duty cycle application information power supply filtering techniques as in any high speed analog circuitry, noise at the power supply pins can degrade performance. to achieve optimum jitter performance, use good power supply isolation practices. figure 8 illustrates a typical filtering scheme. because all current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. a 0.01 or 0.1 f ceramic chip capacitor is also located close to this pin to provide a short and low impedance ac path to ground. a 1 to 10 f ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. figure 8. power supply filtering termination for lvpecl output the cy2xp24 implements its lvpecl driver with a current steering design. for proper opera tion, it requires a 50 ohm dc termination on each of the two output signals. for 3.3 v operation, this data sheet specifies output levels for termination to v dd ?2.0 v. this termination voltage can also be used for v dd = 2.5 v operation, or it can be terminated to v dd -1.5 v. note that it is also possible to terminate with 50 ohms to ground (v ss ), but the high and low signal levels differ from the data sheet values. termination resistors are best located close to the destination device. to avoid reflections, trace characteristic impedance (z 0 ) should match the termination impedance. figure 9 shows a standard termination scheme. figure 9. lvpecl output termination crystal input interface the cy2xp24 is characterized with 18 pf parallel resonant crystals. the capacitor values shown in figure 10 are determined using a 25 mhz 18 pf parallel resonant crystal and are chosen to minimize the pp m error. note that the optimal values for c1 and c2 depend on the parasitic trace capacitance and are therefore layout dependent. figure 10. crystal input interface clk t pw t period t dc = t pw t period clk# 3.3v 10 f ???? f v dd v dd 0.01 f (pin 1) (pin 8) clk 84 ? 84 ? z0 = 50 ? z0 = 50 ? 3.3v 125 ? 125 ? in clk# device xin xout x1 18 pf parallel crystal c1 30 pf c2 27 pf [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 8 of 12 ordering code definition ordering information part number package type product flow cy2xp24zxc 8-pin tssop commercial, 0 ? c to 70 ? c cy2xp24zxct 8-pin tssop?tape and reel commercial, 0 ? c to 70 ? c CY2XP24ZXI 8-pin tssop industrial, -40 ? c to 85 ? c CY2XP24ZXIt 8-pin tssop?tape and reel industrial, -40 ? c to 85 ? c t = tape and reel temperature range : c = commercial, i = industrial pb-free package type part identifier family company id: cy = cypress xx cy xxxx z x t c/i [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 9 of 12 package drawing and dimensions figure 11. 8-pin thin shrunk sm all outline package (4.40 mm body) z8 51-85093 *c [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 10 of 12 acronyms document conventions units of measure acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map eprom erasable programmab le read only memory lvds low-voltage differential signaling lvpecl low voltage positive emitter coupled logic ntsc national televi sion system committee oe output enable pal phase alternate line pd power down pll phase locked loop ppm parts per million ttl transistor transistor logic symbol unit of measure c degrees celsius khz kilohertz k ? kilohms mhz megahertz m ? megaohms a microamperes s microseconds v microvolts vrms microvolts root-mean-square ma milliamperes mm millimeters ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ? ohms [+] feedback
cy2xp24 document #: 001-15705 rev. *g page 11 of 12 document history page document title: cy2xp24 cryst al to lvpecl clock generator document number: 001-15705 rev. ecn no. submission date orig. of change description of change ** 1285703 see ecn wwz/kvm/ ari new data sheet *a 1451704 see ecn wwz/aesa added i-temp devices *b 2669117 03/05/2009 kvm/aesa changed crystal frequency and output frequencies updated phase jitter value rise & fall times changed from 350 ps to 500 ps (typ.) junction temperature changed from 125 ? c to 135 ? c changed iil and iih values entered value for idd removed msl spec changed data sheet status to final *c 2700242 04/30/2009 kvm/pyrs typos: changed vcc to vdd, changed ps to mhz changed footnote about external power dissipation reformatted ac and dc tables changed lvpecl parameters from vpp to vod and vocm added cinx spec added idd for 2.5v added tlock timing revised text in applicat ion information section changed recommended crystal load capacitor values *d 2718433 06/12/2009 wwz/hmt no change. submit to ecn for product launch. *e 2767308 09/22/2009 kvm add phase jitter spec for 12 khz - 20 mhz integration range add i dd spec for unterminated outputs change parameter name for i dd (terminated outputs) from i dd to i ddt remove i dd footnote about extern ally dissipated current add footnote reference to c in and c inx :not 100% tested add max limit for t r , t f : 1.0 ns change t lock max from 10 ms to 5 ms split out parameter t lfs from t lock *f 2896121 03/19/2010 kvm updated package diagram (figure 11) *g 3218841 03/07/2011 bash updated as per template added acronyms and units of measure table added ordering code definition details updated package diagram 51-85093 from *b to *c [+] feedback
document #: 001-15705 rev. *g revised april 7, 2011 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2xp24 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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